1. Technical Field
The invention disclosed broadly relates to semiconductor devices and circuits and more particularly relates to an improved integrated circuit which is immune to single event upsets.
2. Background Art
As the number of devices in a very large scale integrated (VLSI) circuit chip surpasses 10.sup.5, the individual transistor devices which form its component elementary logic circuits, occupy areas of the chip on the order of a few square microns. The quantity of charge which is transferred between field effect transistor devices of this size while carrying out normal switching operations, in on the order of 0.1 picoCoulombs (10.sup.-12 Colombs), making them very susceptible to electrostatic perturbations.
One ubiquitous source of such perturbations is cosmic rays, a highly penetrating radiation apparently reaching the earth in all directions from outer space. The primary cosmic rays entering the earth's atmosphere are almost entirely composed of positively charged atomic nuclei which collide with air nuclei high in the atmosphere, forming showers of positively and negatively charged nuclear fragments called secondary cosmic rays. These secondary cosmic rays penetrate all matter at the earth's surface and as they pass through a material object, they undergo collisions with electrons and nuclei of which the material is composed, leaving a track of electrostatic charge along the way. The linear charge density along such a track can be typically 0.3 picoCoulombs per micron, which is on the same scale as the quantity of charge involved in the switching operation of a single field effect transistor on a VLSI chip.
This becomes a significant problem in latch circuits composed of such devices, since a latch must sense and reliably store a binary bit of information for intervals measurable in millions of machine cycles. In order to better understand this problem, reference will be made to a typical integrated circuit field effect transistor latch and the mechanism of its response to an electrostatic perturbation such as a cosmic ray, will be discussed.
To begin this description, several terms need to be defined and suitable abbreviations established. The N channel field effect transistor circuit technology will be the example used herein. The abbreviation NFET will be used herein to refer to an N channel field effect transistor device. Such devices are generally fabricated by forming an N-type conductivity source diffusion and N-type drain diffusion in the surface of a P-type conductivity silicon substrate. The channel region of the substrate separating the source and drain regions, is covered by a gate insulator layer and a gate electrode. An enhancement mode NFET is normally nonconducting between its source and drain and it can be switched into conduction by applying a positive potential to its gate electrode, with respect to the potential of its source. A depletion mode NFET is normally conducting between its source and drain and it can be switched into nonconduction by applying a negative potential to its gate electrode, with respect to the potential of its source.
The abbreviation PFET will be used herein to refer to a P channel field effect transistor device. Such devices are generally fabricated by forming P-type conductivity source diffusion and P-type conductivity drain diffusions within an N-type conductivity diffusion called an N-well which, in turn, has been formed in the P-type semiconductor substrate for the integrated circuit. The channel region of the N-well separating the P-type source and drain diffusions is covered by the gate insulator layer and the gate electrode. An enhancement mode PFET is normally nonconducting between a source and drain when the gate-to-source potential is relatively negative, the opposite condition from that obtaining from an NFET device relative biasing.
One prior art approach to solving the single event upset problem for N channel enhancement mode/depletion mode flip-flop storage cells is described in U.S. Pat. No. 4,638,463 to L. R. Rockett, entitled "Fast Writing Circuit for a Soft Error Protected Storage Cell," issued Jan. 20, 1987 and assigned to the IBM Corporation. The principle of operation of the circuits disclosed in this earlier patent work well for enhancement mode/depletion mode circuit technology, however the problem of reducing the effect of single event upsets on complementary MOS (CMOS) circuits still remains significant. As used herein, CMOS refers to integrated circuits which employ both PFET and NFET devices connected so as to provide high speed, low power dissipation, integrated circuits for logic and memory applications.
Another prior art approach to reducing the effect of a single event upset in disturbing the stored state in an NFET flip-flop storage cell, is to provide a resistive element in the cross-coupling connection between the respective storage nodes of the cell. The purpose of the resistive element is to prevent the flow of charge from one node to the other node during the single event upset condition, thereby reducing the chances that the state of the cell will be disturbed. However, a significant disadvantage of such a prior art configuration is the reduction in the speed of operation of the flip-flop storage cell during normal write mode operations. The presence of the resistive device will increase the amount of time necessary to change the state of the flip-flop cell from a first binary state to a second binary state by flowing current from one node to the other node. It is this problem which is addressed by the invention disclosed and claimed herein.